A Buffer‐Sizing Algorithm for Network‐on‐Chips with Multiple Voltage‐Frequency Islands

Buffers in on-chip networks constitute a significantproportion of the power consumption and area of theinterconnect, and hence reducing them is an important problem.Application-specific designs have nonuniform networkutilization, thereby requiring a buffer-sizing approach thattackles the nonuniformity. Also, congestion effects that occurduring network operation need to be captured when sizing thebuffers. Many NoCs are designed to operate in multiple voltage/frequency islands, with interisland communication takingplace through frequency converters. To this end, we proposea two-phase algorithm to size the switch buffers in network-on-chips (NoCs) considering support for multiple-frequencyislands. Our algorithm considers both the static and dynamiceffects when sizing buffers. We analyze the impact of placingfrequency converters (FCs) on a link, as well as pack and sendunits that effectively utilize network bandwidth. Experimentson many realistic system-on-Chip (SoC) benchmark showthat our algorithm results in 42% reduction in amount ofbuffering when compared to a standard buffering approach