English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Tools annual

Global: Zendy Free Plan

Global: Zendy Tools monthly

Global: Zendy Plus monthly

The design and CMOS implementation of Multi-Processor System-on-Chip (MPSoC) architectures for real-time multimedia signal processing is discussed in the paper. Two multi-tile architectures are proposed and compared with reference to audio and video processing target applications. One architecture exploits an homogeneous topology; it consists of 8 identical tiles, each made of a 32-bit RISC core enhanced by a 64-bit DSP co-processor with local memory resources. The other multi-core architecture exploits an heterogeneous-tile topology with on-chip distributed memory resources; the tiles act as application specific processors (ASIPs) supporting different class of algorithms. Since the ASIP tiles can work concurrently, then a large set of processing algorithms is supported. In both architectures the multiple tiles are interconnected by a Network-on-Chip (NoC) infrastructure with Spidergon topology through Network Interfaces (NIs) and Routers. The packet-switched data transfer scheme of NoC allows parallel operations of the multiple tiles. The functional performances and the implementation complexity (area, power) of the NoC-based MPSoC architectures are assessed by presenting the achieved results when the platforms are synthesized in submicron CMOS technology. Among the large set of supported algorithms, two example case studies are considered: the real-time implementation of a H.264/MPEG AVC video codec and of a low-distortion digital audio amplifier. The heterogeneous architecture ensures a higher power efficiency and a smaller area occupation. The homogeneous scheme allows for a higher flexibility and easier system scalability since the tiles are the same and offer more general purpose computation resources. The heterogeneous MPSoC is more suited for low-power multimedia processing, such as in mobile devices; the homogeneous MPSoC is more suited for general purpose DSP tasks in power-supplied devices

Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing