Modeling and Implementation of a Power Estimation Methodology for SystemC

This work describes a methodology to model powerconsumption of logic modules. A detailed mathematical modelis presented and incorporated in a tool for translation ofmodels written in VHDL to SystemC. The functionality forimplicit power monitoring and estimation is inserted at moduletranslation. The translation further implements an approach towrap RTL to TLM interfaces so that the translated module canbe connected to a system-level simulator. The power analysis isbased on a statistical model of the underlying HW structureand an analysis of input data. The flexibility of the C++syntax is exploited, to integrate the power evaluation technique. The accuracy and speed-up of the approach are illustrated andcompared to a conventional power analysis flow using PPRsimulation, based on Xilinx technology