Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based System Designs Accelerated by FPGA Logic | Zendy

Michael Schaeferling | Zendy; Ulrich Hornung | Zendy; Gundolf Kiefer | Zendy

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Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based System Designs Accelerated by FPGA Logic

Author(s) -

Michael Schaeferling,

Ulrich Hornung,

Gundolf Kiefer

Publication year - 2012

Publication title -

international journal of reconfigurable computing

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.236

H-Index - 16

eISSN - 1687-7209

pISSN - 1687-7195

DOI - 10.1155/2012/368351

Subject(s) - field programmable gate array , computer science , pose , feature (linguistics) , object (grammar) , object detection , virtex , artificial intelligence , computer vision , microcontroller , cognitive neuroscience of visual object recognition , point (geometry) , augmented reality , computer hardware , embedded system , pattern recognition (psychology) , philosophy , linguistics , geometry , mathematics

State-of-the-art object recognition and pose estimationsystems often utilize point feature algorithms, which inturn usually require the computing power of conventional PChardware. In this paper, we describe two embedded systems forobject detection and pose estimation using sophisticated pointfeatures. The feature detection step of the “Speeded-up RobustFeatures (SURF)” algorithm is accelerated by a special IP core. The first system performs object detection and is completelyimplemented in a single medium-size Virtex-5 FPGA. The secondsystem is an augmented reality platform, which consists of anARM-based microcontroller and intelligent FPGA-based cameraswhich support the main system

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