9T Full Adder Design in Subthreshold Region | Zendy

Shiwani Singh | Zendy; Tripti Sharma | Zendy; K. G. Sharma | Zendy; Bharat Singh | Zendy

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9T Full Adder Design in Subthreshold Region

Author(s) -

Shiwani Singh,

Tripti Sharma,

K. G. Sharma,

Bharat Singh

Publication year - 2012

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/2012/248347

Subject(s) - adder , subthreshold conduction , power–delay product , computer science , electronic engineering , power (physics) , logic gate , transistor , electrical engineering , voltage , algorithm , engineering , cmos , physics , quantum mechanics

This paper presents prelayout simulations of two existing 9T and new proposed 9T full adder circuit in subthreshold region to employ in ultralow-power applications. The proposed circuit consists of a new logic which is used to implement Sum module. The proposed design remarkably reduces power-delay product (PDP) and improves temperature sustainability when compared with existing 9T adders. Therefore, in a nut shell proposed adder cell outperforms the existing adders in subthreshold region and proves to be a viable option for ultralow-power and energy-efficient applications. All simulations are performed on 45nm standard model on Tanner EDA tool version 13.0.

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