VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation

We present a novel approach for the on-chip generation of a fault-tolerant clock. Our method is based on thehardware implementation of a tick synchronization algorithm from the distributed systems community. We discussthe selection of an appropriate algorithm, present the refinement steps necessary to facilitate its efficient mappingto hardware, and elaborate on the key challenges we had to overcome in our actual ASIC implementation. Ourmeasurement results confirm that the approach is indeed capable of creating a globally synchronized clock in adistributed fashion that is tolerant to a (configurable) number of arbitrary faults. This property facilitates eliminatingthe clock as a single point of failure. Our solution is based on purely asynchronous design, obviating the need forcrystal oscillators. It is capable of adapting to parameter variations as well as changes in temperature and powersupply–properties that are considered highly desirable for future technology nodes