FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study | Zendy

Tobias Schumacher | Zendy; Tim Süß | Zendy; Christian Plessl | Zendy; Marco Platzner | Zendy

Open Access

FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study

Author(s) -

Tobias Schumacher,

Tim Süß,

Christian Plessl,

Marco Platzner

Publication year - 2011

Publication title -

international journal of reconfigurable computing

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.236

H-Index - 16

eISSN - 1687-7209

pISSN - 1687-7195

DOI - 10.1155/2011/760954

Subject(s) - computer science , key (lock) , computer architecture , compositing , benchmarking , host (biology) , field programmable gate array , hardware acceleration , frame (networking) , frame rate , architecture , computer hardware , embedded system , image (mathematics) , operating system , computer network , artificial intelligence , ecology , marketing , business , biology , art , visual arts

Reconfigurable computers usually provide a limitednumber of different memory resources, such as hostmemory, external memory, and on-chip memory with differentcapacities and communication characteristics. A keychallenge for achieving high-performance with reconfigurableaccelerators is the efficient utilization of the available memoryresources. A detailed knowledge of the memories' parametersis key for generating an optimized communication layout. In this paper, we discuss a benchmarking environmentfor generating such a characterization. The environment isbuilt on IMORC, our architectural template and on-chipnetwork for creating reconfigurable accelerators. We providea characterization of the memory resources available on theXtremeData XD1000 reconfigurable computer. Based on thisdata, we present as a case study the implementation of a 3Dimage compositing accelerator that is able to double the frame rateof a parallel renderer

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