A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs

In FPGA embedded systems, designers usually have to make a compromise between numerical precision and logical resources. Scientific computations in particular, usually requirehighly accurate calculations and are computing intensive. In this context, a designer is left with the task of implementing severalarithmetic cores for parallel processing while supporting high numerical precision with finite logical resources.This paper introduces an arithmetic architecture that uses runtime partial reconfiguration to dynamically adapt its numericalprecision, without requiring significant additional logical resources. The paper also quantifies the relationship betweenreduced logical resources and savings in power consumption, which is particularly important for FPGA implementations. Finally, our results show performance benefits when this approach is compared to alternative static solutions within bounds on the reconfiguration rate