A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback

Dynamically reconfigurable computing platforms provide promisingmethods for dynamic management of hardware resources, power, andperformance. Yet, progress in dynamically reconfigurable computingis fundamentally limited by the reconfiguration time overhead.Prior research in the development of dynamic partialreconfiguration (DPR) controllers has been limited by its use ofthe Processor Local Bus (PLB). As a result, the bus wasunavailable during DPR. This resulted in significant timeoverhead. To minimize the overhead, we introduce the use of amultiport memory controller (MPMC) that frees the PLB during thereconfiguration process. The processor is thus allowed to switchto other tasks during the reconfiguration operation. Thiseffectively limits the reconfiguration overhead. An interrupt isused to inform the processor when the operation is complete.Therefore, the system can multitask during the reconfigurationoperation. Furthermore, to maximize performance, we introduce theuse of overclocking with active feedback. During overclocking, theuse of active feedback is used to ensure that the device voltageand temperature are within nominal operating conditions. All ofthese contributions lead to significant performance improvementsover current partial reconfiguration subsystems. The portabilityof the system, demonstrated on the Virtex-4 and the Virtex-5,consists of four different hardware platforms