Open AccessA High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos
Author(s) -
Marcel Corrêa,
Mateus Thurow Schoenknecht,
Robson Dornelles,
Luciano Agostini
Publication year - 2010
Publication title -
international journal of reconfigurable computing
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.236
H-Index - 16
eISSN - 1687-7209
pISSN - 1687-7195
DOI - 10.1155/2011/254730
Subject(s) - computer science , field programmable gate array , throughput , key (lock) , interpolation (computer graphics) , pixel , motion estimation , vhdl , process (computing) , hardware architecture , architecture , computer hardware , frame rate , computer architecture , embedded system , motion (physics) , artificial intelligence , software , art , telecommunications , visual arts , computer security , wireless , programming language , operating system
This paper presents a high-performance hardware architecture for the H.264/AVC Half-Pixel Motion Estimation that targets high-definition videos. This design can process very high-definition videos like QHDTV (3840×2048) in real time (30 frames per second). It also presents an optimized arrangement of interpolated samples, which is the main key to achieve an efficient search. The interpolation process is interleaved with the SAD calculation and comparison, allowing the high throughput. The architecture was fully described in VHDL, synthesized for two different Xilinx FPGA devices, and it achieved very good results when compared to related works
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