Semidigital PLL Design for Low-Cost Low-Power Clock Generation | Zendy

Ni Xu | Zendy; Woogeun Rhee | Zendy; Zhihua Wang | Zendy

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Semidigital PLL Design for Low-Cost Low-Power Clock Generation

Author(s) -

Ni Xu,

Woogeun Rhee,

Zhihua Wang

Publication year - 2011

Publication title -

journal of electrical and computer engineering

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.318

H-Index - 25

eISSN - 2090-0155

pISSN - 2090-0147

DOI - 10.1155/2011/235843

Subject(s) - phase locked loop , cmos , pll multibit , scalability , electronic engineering , power (physics) , computer science , engineering , embedded system , jitter , physics , quantum mechanics , database

This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively

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