Open AccessHigh-Speed FPGA 10's Complement Adders-Subtractors
Author(s) -
Géry Jean Antoine Bioul,
Martín Vázquez,
JeanPierre Deschamps,
Gustavo Sutter
Publication year - 2010
Publication title -
international journal of reconfigurable computing
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.236
H-Index - 16
eISSN - 1687-7209
pISSN - 1687-7195
DOI - 10.1155/2010/219764
Subject(s) - adder , computer science , field programmable gate array , carry (investment) , decimal , subtractor , virtex , parallel computing , arithmetic , carry save adder , serial binary adder , computer hardware , complement (music) , operand , mathematics , latency (audio) , telecommunications , finance , economics , biochemistry , chemistry , complementation , gene , phenotype
This paper first presents a study on the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGA's platforms. Some new concepts are presented to compute the P and G functions for carry-chain optimization purposes. Several alternative designs are presented. Then, attention is given to FPGA implementations of add/subtract algorithms for 10's complement BCD numbers. Carry-chain type circuits have been designed on 4-input LUTs (Virtex-4, Spartan-3) and 6-input LUTs (Virtex-5) Xilinx FPGA platforms. All designs are presented with the corresponding time performance and area consumption figures. Results have been compared to straight implementations of a decimal ripple-carry adder and an FPGA 2's complement binary adder-subtractor using the dedicated carry logic, both carried out on the same platform. Better time delays have been registered for decimal numbers within the same range of operands
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