Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs | Zendy

Gabriel Caffarena | Zendy; Juan Antonio López Martín | Zendy; Gerardo LeyvaGómez | Zendy; Carlos Carreras | Zendy; Octavio Nieto-Taladriz | Zendy

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Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs

Author(s) -

Gabriel Caffarena,

Juan Antonio López Martín,

Gerardo LeyvaGómez,

Carlos Carreras,

Octavio Nieto-Taladriz

Publication year - 2009

Publication title -

international journal of reconfigurable computing

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.236

H-Index - 16

eISSN - 1687-7209

pISSN - 1687-7195

DOI - 10.1155/2009/703267

Subject(s) - datapath , field programmable gate array , computer science , digital signal processing , multiplexer , embedded system , high level synthesis , reconfigurable computing , computer architecture , computer hardware , parallel computing , multiplexing , telecommunications

We address the automatic synthesis of DSP algorithms using FPGAs. Optimized fixed-point implementations are obtained by means of considering (i) a multiple wordlength approach; (ii) a complete datapathformed of wordlength-wise resources (i.e., functional units, multiplexers, and registers); (iii) an FPGA-wise resourceusage metric that enables an efficient distribution of logic fabric and embedded DSP resources.The paper shows (i) the benefits of applying a multiple wordlength approach to the implementation of fixed-pointdatapaths and (ii) the benefits of a wise use of embedded FPGA resources. The use of a complete fixed-point datapathleads to improvements up to 35%. And, the wise mapping of operations to FPGA resources (logic fabric and embeddedblocks), thanks to the proposed resource usage metric, leads to improvements up to 54%

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