FPGA Interconnect Topologies Exploration

International audienceThis paper presents an improved interconnect network forTree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed toplace and route the largest benchmark circuits, where different optimization techniques are used to get an optimizedarchitecture. The effect of variation in LUT and cluster size on the area, performance, and power of the Tree-based architecture is analyzed. Experimental results show that an architecture with LUT size 4 and arity size 4 is the most efficient in terms of area and static power dissipation, whereas the architectures with higher LUT and cluster size are efficient in terms of performance. We also show that unifying a Mesh with this Tree topology leads to an architecture which has good layout scalability and better interconnect efficiencycompared to VPR-style Mesh