Fully Pipelined Parallel Architecture for Candidate Block and Pixel-Subsampling-Based Motion Estimation | Zendy

Reeba Korah | Zendy; J. Raja Paul Perinbam | Zendy

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Fully Pipelined Parallel Architecture for Candidate Block and Pixel-Subsampling-Based Motion Estimation

Author(s) -

Reeba Korah,

J. Raja Paul Perinbam

Publication year - 2008

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/2008/890410

Subject(s) - block (permutation group theory) , motion vector , computer science , pixel , motion estimation , clock rate , power consumption , parallel architecture , block size , architecture , parallel computing , power (physics) , degradation (telecommunications) , computer hardware , algorithm , computer engineering , artificial intelligence , image (mathematics) , key (lock) , mathematics , telecommunications , art , chip , physics , geometry , visual arts , computer security , quantum mechanics

This paper presents a low power and high speed architecture for motion estimation with Candidate Block and Pixel Subsampling (CBPS) Algorithm. Coarse-to-fine search approach is employed to find the motion vector so that the local minima problem is totally eliminated. Pixel subsampling is performed in the selected candidate blocks which significantly reduces computational cost with low quality degradation. The architecture developed is a fully pipelined parallel design with 9 processing elements. Two different methods are deployed to reduce the power consumption, parallel and pipelined implementation and parallel accessing to memory. For processing 30 CIF frames per second our architecture requires a clock frequency of 4.5 MHz

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