High-Performance Timing-Driven Rank Filter | Zendy

Péter Szántó | Zendy; Gábor Szedő | Zendy; Béla Fehér | Zendy

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High-Performance Timing-Driven Rank Filter

Author(s) -

Péter Szántó,

Gábor Szedő,

Béla Fehér

Publication year - 2008

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/2008/753043

Subject(s) - field programmable gate array , rank (graph theory) , computer science , filter (signal processing) , exploit , computer engineering , architecture , image (mathematics) , computer architecture , algorithm , computer hardware , artificial intelligence , real time computing , computer vision , mathematics , art , computer security , combinatorics , visual arts

This paper presents an FPGA implementation of a high-performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoffs between complexity and performance. By maximizing the operating frequency, the complexity of the filter structure can be considerably reduced compared to previous 2D architectures

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