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This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area whentargeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thusallowing a designer to concentrate more on an algorithm description and less on hardware-specific implementationdetails. The first algorithm is a source-level transformation implementing function exlining—where a separate block of hardware implements a function and is shared between multiple calls to thefunction. The second is a novel algorithm for mapping arrays to memories which involves assigning arrayaccesses to memory ports such that no port is ever accessed more than once in a clock cycle. This algorithmassigns accesses to read/write only ports and read-write ports concurrently, solving the assignment problemmore efficiently for a wider range of memories compared to existing methods. Both optimisations operateon a high-level program representation and have been implemented in a commercial SystemC compiler.Experiments show that in suitable circumstances these techniques result in significant reductions in logicutilisation for FPGAs

Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation