A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators | Zendy

Tzung-Je Lee | Zendy; ChuaChin Wang | Zendy

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A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators

Author(s) -

Tzung-Je Lee,

ChuaChin Wang

Publication year - 2008

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/2008/512946

Subject(s) - jitter , phase locked loop , voltage controlled oscillator , phase noise , cmos , noise (video) , loop (graph theory) , voltage , electronic engineering , pll multibit , power consumption , control theory (sociology) , charge pump , power (physics) , regulator , computer science , electrical engineering , physics , mathematics , engineering , capacitor , artificial intelligence , chemistry , image (mathematics) , biochemistry , control (management) , quantum mechanics , combinatorics , gene

A phase-locked loop (PLL) using separate regulators to reject the supply noise is proposed in this paper. Two regulators, REG1 and REG2, are used to prevent the supply noise from the charge pump (CP) and the voltage-controlled oscillator (VCO), respectively. By using separate regulators, the area and the power consumption of the regulator can be reduced. Moreover, the jitter of the proposed PLL is proven on silicon to be less sensitive to the supply noise. The proposed PLL is fabricated using a typical 0.35 μm 2P4M CMOS process. The peak-to-peak jitter (P2P jitter) of the proposed PLL is measured to be 81.8 ps at 80 MHz when a 250 mVrms supply noise is added. By contrast, the P2P jitter is measured to be 118.2 ps without the two regulators when the same supply noise is coupled

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