Open AccessA Programmable Max-Log-MAP Turbo Decoder Implementation
Author(s) -
Perttu Salmela,
Harri Sorokin,
Jarmo Takala
Publication year - 2008
Publication title -
vlsi design
Language(s) - English
Resource type - Journals
eISSN - 1065-514X
pISSN - 1026-7123
DOI - 10.1155/2008/319095
Subject(s) - turbo , computer science , turbo code , turbo equalizer , soft decision decoder , decoding methods , computer hardware , clock rate , interface (matter) , set (abstract data type) , trellis (graph) , parallel computing , real time computing , algorithm , chip , concatenated error correction code , engineering , telecommunications , bubble , maximum bubble pressure method , automotive engineering , programming language , block code
In the advent of very high data rates of the upcoming 3G long-term evolution telecommunication systems, there is a crucial need for efficient and flexible turbo decoder implementations. In this study, a max-log-MAP turbo decoder is implemented as an application-specific instruction-set processor. The processor is accompanied with accelerating computing units, which can be controlled in detail. With a novel memory interface, the dual-port memory for extrinsic information is avoided. As a result, processing one trellis stage with max-log-MAP algorithm takes only 1.02 clock cycles on average, which is comparable to pure hardware decoders. With six turbo iterations and 277 MHz clock frequency 22.7 Mbps, decoding speed is achieved on 130 nm technology
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