Design of a VLSI Decoder for Partially Structured LDPC Codes | Zendy

F. Vacca | Zendy; Libero Dinoi | Zendy; Guido Masera | Zendy

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Design of a VLSI Decoder for Partially Structured LDPC Codes

Author(s) -

F. Vacca,

Libero Dinoi,

Guido Masera

Publication year - 2008

Publication title -

international journal of digital multimedia broadcasting

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.164

H-Index - 17

eISSN - 1687-7586

pISSN - 1687-7578

DOI - 10.1155/2008/245305

Subject(s) - computer science , very large scale integration , decoding methods , low density parity check code , constructive , parity check matrix , class (philosophy) , algorithm , process (computing) , embedded system , artificial intelligence , operating system

The starting point of this work is the development of a new class of partially structured LDPC codes, very well suited for hardware implementation. Specifically these codes are built so that the edgesof their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized

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