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The severity of power consumption during parallel BIST of embedded memory	 cores is growing significantly. In order to alleviate this problem, a row bank-based precharge 	 technique based on the divided wordline (DWL) architecture is proposed for low-power testing of embedded	  SRAMs. The memory cell array is first divided into row banks. The effectiveness of the row 	  bank-based precharge technique  is due to the predictable address sequence during test. In low-power test 	  mode, instead of precharging the entire memory array, only the current accessed row bank is	   precharged. This will result in significant power saving for the precharge circuitry. The precharge power	    can be reduced to 1/b of that of the traditional precharge techniques, where b denotes the number of row banks in the memory array. With simple transmission gates and inverters, the modified precharge control circuitry was also designed. The hardware overhead for implementing the low-power technique is almost negligible. Moreover, the corresponding BIST design to implement the low-power technique is almost the same as the conventional BIST  designs. It is also notable that the inherent low-power characteristics of the DWL architecture can  be preserved. According to experimental results, 48.9% power reduction can be achieved for  a 256 × 256 bit-oriented SRAM. The memory is divided into 8 row banks. Moreover, if the number of row banks increases, the power saving will also increase

Low-Power Built-In Self-Test Techniques for Embedded SRAMs