A Video Specific Instruction Set Architecture for ASIP design | Zendy

Zheng Shen | Zendy; Hu He | Zendy; Yanjun Zhang | Zendy; Yihe Sun | Zendy

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A Video Specific Instruction Set Architecture for ASIP design

Author(s) -

Zheng Shen,

Hu He,

Yanjun Zhang,

Yihe Sun

Publication year - 2007

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/2007/58431

Subject(s) - simd , computer science , instruction set , computer architecture , coding (social sciences) , set (abstract data type) , architecture , encoding (memory) , context (archaeology) , digital signal processing , parallel computing , multimedia , computer hardware , artificial intelligence , art , paleontology , statistics , mathematics , visual arts , biology , programming language

This paper describes a novel video specific instruction set architecture for ASIP design. With single instruction multiple data (SIMD) instructions, two destination modes, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS-ISA, other DSPs (digital signal processors), and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS-ISA improves the processor's performance by approximately 5x on H.263 encoding, and VS-ISA outperforms other architectures by 1.6x to 8.57x in computing IDCT

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