Power Consumption and BER of Flip-Flop Inserted Global Interconnect

In nanometer scale integrated circuits, concurrent insertion of repeaters and sequential elements into the global interconnect lines has been proposed to support multicycle communication—a concept known as interconnect pipelining. The design targets of an interconnect-pipelining scheme are to ensure high reliability, low-power consumption, and less delay cycles. This paper presents an in-depth analysis of the reliability in terms of bit error rate (BER) and the power consumption of wire-pipelining scheme. In this analysis, the dependencies of power consumption and BER on the number of inserted flip-flops,and the size of repeaters are illustrated. To trade off the design targets (wire delay, BER,and power consumption), a methodology is developed to optimize the repeater size andthe number of flip-flops inserted which maximize a user-specified figure of merit.The methodology is demonstrated by calculating optimal solutions for interconnect pipeliningfor some International Technology Roadmap for Semiconductor technology nodes