A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits | Zendy

Rong Lin | Zendy

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A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits

Author(s) -

Rong Lin

Publication year - 2000

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/2001/97598

Subject(s) - multiplier (economics) , adder , binary number , electronic circuit , arithmetic , logic gate , sequential logic , computer science , mathematics , cmos , electronic engineering , algorithm , electrical engineering , engineering , economics , macroeconomics

A highly regular parallel multiplier architecture along with the novel low-power, high-performanceCMOS implementation circuits is presented. The superiority is achievedthrough utilizing a unique scheme for recursive decomposition of partial productmatrices and a recently proposed non-binary arithmetic logic as well as thecomplementary shift switch logic circuits

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