Open AccessA Fast Algorithm for Transistor Folding
Author(s) -
Edward Y. Cheng,
Sartaj Sahni
Publication year - 1999
Publication title -
vlsi design
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.123
H-Index - 24
eISSN - 1065-514X
pISSN - 1026-7123
DOI - 10.1155/2001/96353
Subject(s) - folding (dsp implementation) , computer science , transistor , algorithm , engineering , electrical engineering , voltage
Transistor folding reduces the area of row-based designs that employ transistors ofdifferent size. Kim and Kang [1] have developed an O(m2 log m) algorithm to optimally fold m transistor pairs. In this paper we develop an O(m2) algorithm for optimal transistor folding. Our experiments indicate that our algorithm runs 3 to 60 times as fastfor m values in the range (100, 100,000)
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