Efficient Low Power/Low Swing Bus Design Architectures

Novel low-power circuits based on low swing voltage technique, in the internal nodes ofbus architectures, are proposed. Different classes of driver/receiver and repeater circuitsare presented. They are implemented on conventional CMOS technology. The proposedtechnique is based on inserting a variable number of MOSFET transistors in the drivercircuits, causing variable low swing voltage levels in the output of the driver circuits. Inorder to re-pull up the low swing voltage to full swing, innovated high-speed, crosscoupledlatch voltage receiver circuits are proposed. In applications having high loadcapacitance due to long interconnections, novel repeater circuits, based also on lowswing voltage technique, are introduced. The difference between the values of thresholdvoltage of the nMOS transistor and the pMOS transistors is exploited to decrease thepower dissipation. The effect of the proposed technique in noise margins is also analysed