On Mixed PTL/Static Logic for Low-power and High-speed Circuits

We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic(PTL) structure that mixes conventional PTL structure with static logic gates canachieve better performance and lower power consumption compared to conventionalPTL structure. The goal is to use the static gates to perform both logic functions as wellas buffering. Our experimental results demonstrate that the proposed mixed PTLstructure beats pure static structure and conventional PTL in 9 out of 15 test cases foreither delay or power consumption or both in a 0.25 μm CMOS process. The averagedelay, power consumption, and power-delay product of the proposed structure for 15test cases are 10% to 20% better of than the pure static implementations and up to 50%better than the conventional PTL implementations