A Size‐optimization Design for Variable Length Coding Using Distributed Logic

In this paper, we first employ an efficient approach to reduce the time to construct acodeword. With this codeword, a novel VLSI architecture is proposed to realize highspeedVariable Length Coding (VLC). In order to combine with other circuits using cell-baseddesign, we adopt distributed logic rather than memory devices (ROM, PLA) forthe implementation. In this architecture, the VLC coding scheme is partitioned into twoparts, one is the codeword length and order index for bit control, another is thecodeword bank for actual codeword generation. The advantage is that the circuit size ofthe proposed method can be reduced, where the transistor count of proposed method isonly 1/2 and 1/4 of that of ROM- based and PLA-based in average, respectively