Test Generators Need to be Modified to Handle CMOS Designs | Zendy

J. Savir | Zendy

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Test Generators Need to be Modified to Handle CMOS Designs

Author(s) -

J. Savir

Publication year - 2000

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/2001/37087

Subject(s) - test vector , redundancy (engineering) , fault coverage , fault detection and isolation , cmos , reliability engineering , set (abstract data type) , computer science , premise , test set , event (particle physics) , automatic test pattern generation , fault (geology) , computer engineering , test (biology) , algorithm , engineering , electronic engineering , artificial intelligence , electrical engineering , electronic circuit , programming language , paleontology , linguistics , actuator , philosophy , seismology , biology , geology , physics , quantum mechanics

CMOS designs have some unique properties that prevent existing test generators fromcomputing a test vector for a fault when one might exist. The problem lies in thepremises laid out on what it takes to detect a stuck-at fault. The basic premise that statesthat it is required to set a line to 0(1) in order to detect a stuck-at 1(0) fault, and thenpropagate the error to an observable point, needs to be re-examined. This is due to theexistence of indeterminate states throughout the logic. The paper distinguishes betweenthe traditional test vector (here called a hard-detect), and a potential test vector (herecalled a soft-detect). Our proposed test set is the union of hard and soft-detects. We alsore-examine the issue of redundancy and show that it needs to be re-defined in order tocomply with CMOS technology behavior

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