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CMOS designs have some unique properties that prevent existing test generators fromcomputing a test vector for a fault when one might exist. The problem lies in thepremises laid out on what it takes to detect a stuck-at fault. The basic premise that statesthat it is required to set a line to 0(1) in order to detect a stuck-at 1(0) fault, and thenpropagate the error to an observable point, needs to be re-examined. This is due to theexistence of indeterminate states throughout the logic. The paper distinguishes betweenthe traditional test vector (here called a hard-detect), and a potential test vector (herecalled a soft-detect). Our proposed test set is the union of hard and soft-detects. We alsore-examine the issue of redundancy and show that it needs to be re-defined in order tocomply with CMOS technology behavior

Test Generators Need to be Modified to Handle CMOS Designs