Automatic FSM Synthesis for Low-power Mixed Synchronous/Asynchronous Implementation

Power consumption in a synchronous FSM (Finite-State Machine) can be reduced bypartitioning it into a number of coupled sub-FSMs where only the part that is involvedin a state transition is clocked. Automatic synthesis of a partitioned FSM includes apartitioning algorithm and sub-FSM synthesis to an implementation architecture. Inthis paper, we first introduce an implementation architecture for partitioned FSMs thatuses gated-clock technique for disabling idle parts of the circuits and asynchronouscontrollers for communication between the sub-FSMs. We then describe a new transformationprocedure for the sub-FSM. The FSM synthesis flow has been automated in aprototype tool that accepts an FSM specification. The tool generates synthesizable RT-levelVHDL code with identical cycle-to-cycle input/output behavior in accordancewith the specification. An average power reduction of 45% has been obtained for a setstandard FSM benchmarks