A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic

We present a new scalable architecture for the realization of fully programmable rankorder filters (ROF). Capacitive Threshold Logic (CTL) gates are utilized for theimplementation of the multi-input programmable majority (voting) functions requiredin the architecture. The CTL-based realization of the majority gates used in the ROFarchitecture allows the filter rank as well as the window size to be user-programmable,using a much smaller silicon area, compared to conventional realizations of digitalmedian filters. The proposed filter architecture is completely modular and scalable, andthe circuit complexity grows only linearly with maximum window size (m) and withword length (n). A prototype of the proposed filter circuit has been designed andfabricated using double-polysilicon 0.8 μm CMOS technology. Detailed post-layoutsimulations and test results of the ROF prototype circuit indicate that the newarchitecture can accommodate sampling clock rates of up to 50 MHz, corresponding toan effective data processing rate of 800 Mb/s for a very large filter with window size 63and word length of 16 bits