An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking | Zendy

Zhen Luo | Zendy; Margaret Martonosi | Zendy; Pranav Ashar | Zendy

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An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking

Author(s) -

Zhen Luo,

Margaret Martonosi,

Pranav Ashar

Publication year - 1999

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/2000/71046

Subject(s) - computer science , very large scale integration , computer architecture , field programmable gate array , flexibility (engineering) , scalability , application specific integrated circuit , software , embedded system , process (computing) , enhanced data rates for gsm evolution , computer hardware , hardware architecture , programming language , operating system , statistics , mathematics , telecommunications

Previous efforts to build hardware accelerators for VLSI layout Design Rule Checking(DRC) were hobbled by the fact that it is often impractical to build a different rulecheckingASIC each time design rules or fabrication processes change. In this paper, wepropose a configurable hardware approach to DRC. It can garner impressive speedupsover software approaches, while retaining the flexibility needed to change the rule checkeras rules or processes change

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