νMOS-based Sorter for Arithmetic Applications | Zendy

Esther Rodriguez–Villegas | Zendy; M.J. Avedillo | Zendy; J.M. Quintana | Zendy; Gloria Huertas | Zendy; A. Rueda | Zendy

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νMOS-based Sorter for Arithmetic Applications

Author(s) -

Esther Rodriguez–Villegas,

M.J. Avedillo,

J.M. Quintana,

Gloria Huertas,

A. Rueda

Publication year - 1999

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/2000/57240

Subject(s) - arithmetic , multiplier (economics) , sorting , computer science , adder , block (permutation group theory) , binary number , electronic circuit , computer architecture , computer hardware , parallel computing , computer engineering , algorithm , mathematics , engineering , electrical engineering , telecommunications , geometry , economics , macroeconomics , latency (audio)

The capabilities of the conceptual link between threshold gates and sorting networks are explored by implementing some arithmetic demonstrators. In particular, both an multiplier and a counter which use a sorter as the main building block have been implemented. Traditional disadvantages of binary sorters such as their hardware intensive nature are avoided by using νMOS circuits. It allows both an improving of previous results for multipliers based on a similar architecture, and to obtain a new type of counter which shows a reduced delay when compared to a conventional implementation.

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