Low Power VLSI Implementation of the DCT on Single Multiplier DSP Processors | Zendy

Shedden Masupe | Zendy; Tughrul Arslan | Zendy

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Low Power VLSI Implementation of the DCT on Single Multiplier DSP Processors

Author(s) -

Shedden Masupe,

Tughrul Arslan

Publication year - 1999

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/2000/34760

Subject(s) - discrete cosine transform , multiplier (economics) , very large scale integration , multiplication (music) , arithmetic , benchmark (surveying) , digital signal processing , mathematics , adder , computer science , trigonometric functions , power (physics) , algorithm , electronic engineering , computer hardware , cmos , embedded system , engineering , artificial intelligence , image (mathematics) , physics , geodesy , combinatorics , quantum mechanics , economics , macroeconomics , geography , geometry

A generic multiplication scheme for the low power VLSI implementation of the DCT isdescribed in this paper. The scheme concurrently processes blocks of cosine coefficientand pixel values during the multiplication procedure, with the aim of reducing the totalswitched capacitance within the multiplier circuit. The cosine coefficients, within eachblock, are manipulated such that some are processed using shift operations only. Theremaining coefficients are presented to the multiplier inputs as a sequence, orderedaccording to bit correlation between successive cosine coefficients. The paper describesthe multiplication scheme, the power evaluation environment used, and presents results,with a number of standard benchmark examples, demonstrating upto 50% power saving

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