Design of MOS-translinear Multiplier/Dividers in Analog VLSI | Zendy

Antonio J. LópezMartín | Zendy; A. Carlosena | Zendy

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Design of MOS-translinear Multiplier/Dividers in Analog VLSI

Author(s) -

Antonio J. LópezMartín,

A. Carlosena

Publication year - 1999

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/2000/21852

Subject(s) - very large scale integration , cmos , multiplier (economics) , electronic engineering , correctness , cascade , computer science , subthreshold conduction , analog multiplier , electronic circuit , engineering , electrical engineering , transistor , algorithm , voltage , analog signal , chemical engineering , digital signal processing , economics , macroeconomics

A general framework for designing current-mode CMOS analog multiplier/dividercircuits based on the cascade connection of a geometric-mean circuit and a squarer/divider is presented. It is shown how both building blocks can be readily obtained froma generic second-order MOS translinear loop. Various implementations are proposed,featuring simplicity, favorable precision and wide dynamic range. They can be successfullyemployed in a wide range of analog VLSI processing tasks. Experimentalresults of two versions, based on stacked and folded MOS-translinear loops and fabricatedin a 2.4-μm CMOS process, are provided in order to verify the correctness ofthe proposed approach

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