Abstract Architecture Representation Using VSPEC

Complex digital systems are often decomposed into architectures very early in the designprocess. Unfortunately, traditional simulation based languages such as VHDL do notallow the impact of these architectural decisions to be evaluated until a complete,simulatable design of the system is available. After a complete design is available,architectural errors are time-consuming and expensive to correct. However, there is analternative to simulation based techniques: formal analysis of abstract architectures atthe requirements level. This paper describes VSBEC'S approach for defining and analyzingabstract architectures. VSBEC is a Larch interface language for VHDL that allows adesigner to specify the requirements of a VHDL entity using the canonical Larchapproach. VHDL structural architectures that instantiate VSPEC entities define abstractarchitectures. These abstract architectures can be evaluated at the requirements level todetermine the impact of architectural decisions. This paper briefly introduces VSPECprovides a formal definition of VSPEC abstract architectures and presents two examplesthat illustrate the architectural definition capabilities of the language