A VLSI Design for Implementation of Transform Domain Adaptive Filters | Zendy

Ali Najafi | Zendy; Behrouz FarhangBoroujeny | Zendy; Ganesh S. Samudra | Zendy

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A VLSI Design for Implementation of Transform Domain Adaptive Filters

Author(s) -

Ali Najafi,

Behrouz FarhangBoroujeny,

Ganesh S. Samudra

Publication year - 1996

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/1999/87231

Subject(s) - computer science , very large scale integration , parallel computing , arithmetic , digital signal processing , digital signal processor , multiplication (music) , transformation (genetics) , multiplier (economics) , binary tree , subtraction , computer hardware , algorithm , embedded system , mathematics , biochemistry , chemistry , macroeconomics , combinatorics , economics , gene

A VLSI implementation of a dedicated digital signal processor is presented. Theprocessor is tailored for efficient implementation of transform domain adaptive filters. Itincorporates a butterfly processor which performs butterfly operation to implement therequired transformation. It is also able to perform complex addition, subtraction andmultiplication. The butterfly processor makes use of a redundant binary tree multiplierwith a recently proposed coding of signed-digit numbers which reduces the number oflevels in the tree by one. An on-chip read only memory holds the transformationcoefficients. The contents of the ROM determine the type of transform. The processorincorporates an ALU to perform integer arithmetic, address calculations andimplementation of circular memory scheme. For fastest accessibility, the essentialvariables of the algorithm are implemented in a register fire

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