Reconfigurable Shift Switching Parallel Comparators | Zendy

R. Lin | Zendy; Stephan Olariu | Zendy

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Reconfigurable Shift Switching Parallel Comparators

Author(s) -

R. Lin,

Stephan Olariu

Publication year - 1999

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/1999/79875

Subject(s) - comparator , computer science , asynchronous communication , very large scale integration , semaphore , domino , process (computing) , electronic circuit , logic family , logic gate , electronic engineering , logic synthesis , parallel computing , computer architecture , embedded system , algorithm , electrical engineering , engineering , telecommunications , biochemistry , chemistry , voltage , catalysis , operating system

We present novel asynchronous VLSI comparator schemes which are based on recentlyproposed, reconfigurable shift switch logic and the traditional (precharged) CMOSdomino logic. The schemes always produce a semaphore as a by-product of the processto indicate the end of domino process, which requires no additional delay and a minimalnumber of additional devices. For a large percentage of inputs the computations aremuch faster than traditional synchronous comparators due to the full utilization of theinherent speed of the circuits. Also the schemes are simple, area compact and stable

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