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Automatic Test Timing Assignment for RAMs Using Linear Programming
Author(s) -
Wen-Jer Wu,
Chuan Tang
Publication year - 1998
Publication title -
vlsi design
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.123
H-Index - 24
eISSN - 1065-514X
pISSN - 1026-7123
DOI - 10.1155/1999/54564
Subject(s) - computer science , asynchronous communication , linear programming , test (biology) , algorithm , biology , computer network , paleontology
[[abstract]]In this paper, an automatic technique for test timing assignment is proposed which is comprehensive enough to take the test objective (e.g., strictness of selected AC timing parameters) and the constraints from both RAM specification and tester into consideration. Since test timing assignment problem could only be solved manually before, therefore, our work can significantly reduce the efforts and costs on developing and maintaining timing modules of RAM test programs. In the proposed technique, the test timing assignment problem is transformed into a linear programming (LP) model, which can be automatically solved. Examples of building LP models for an asynchronous DRAM are given to show feasibility of the proposed technique.[[fileno]]2030209010069[[department]]資訊工程學

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