Influence of BJT Transit Frequency Limit Relation to MOSFET Parameters on the Switching Speed of BiCMOS Digital Circuits
Author(s) -
A. Srivastava
Publication year - 1997
Publication title -
vlsi design
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.123
H-Index - 24
eISSN - 1065-514X
pISSN - 1026-7123
DOI - 10.1155/1999/52841
Subject(s) - bicmos , bipolar junction transistor , spice , electronic engineering , limit (mathematics) , electronic circuit , mosfet , electrical engineering , engineering , transistor , mathematics , voltage , mathematical analysis
The use is made of the BJT transit frequency limit (fTL) dependence on the MOSFET parameters (L, Vth) to design BiCMOS digital circuits. The fTL relation is used in conjunction with the established BiCMOS gate delay models. It is shown that the minimum delay BiCMOS circuits driving the large capacitive load, can be designed at the transit frequency limit with the reduced BJT AREA factor. The time delay calculations are presented for a typical BiCMOS circuit and comparison is made with the results simulated using SPICE.
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