Hierarchy Restructuring for Hierarchical LVS Comparison | Zendy

Wonjong Kim | Zendy; Hyunchul Shin | Zendy

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Hierarchy Restructuring for Hierarchical LVS Comparison

Author(s) -

Wonjong Kim,

Hyunchul Shin

Publication year - 1998

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/1999/50892

Subject(s) - netlist , hierarchy , schematic , computer science , preprocessor , matching (statistics) , hierarchical database model , hierarchical control system , simple (philosophy) , theoretical computer science , algorithm , parallel computing , computer engineering , data mining , artificial intelligence , computer hardware , engineering , mathematics , electronic engineering , philosophy , statistics , control (management) , epistemology , economics , market economy

A new hierarchical layout vs. schematic (LVS) comparison system for layout verificationhas been developed. The schematic hierarchy is restructured to remove ambiguities forconsistent hierarchical matching. Then the circuit hierarchy is reconstructed from thelayout netlist by using a modified SubGemini algorithm recursively in bottom-up fashion.For efficiency, simple gates are found by using a fast rule-based pattern matchingalgorithm during preprocessing. Experimental results show that our hierarchical netlistcomparison technique is effective and efficient in CPU time and in memory usage,especially when the circuit is large and hierarchically structured

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