Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs

Interconnect tuning is an increasingly critical degree of freedom in the physical design ofhigh-performance VLSI systems. By interconnect tuning, we refer to the selection of linethicknesses, widths and spacings in multi-layer interconnect to simultaneously optimizesignal distribution, signal performance, signal integrity, and interconnect manufacturabilityand reliability. This is a key activity in most leading-edge design projects, but hasreceived little attention in the literature. Our work provides the first technology-specificstudies of interconnect tuning in the literature. We center on global wiring layers andinterconnect tuning issues related to bus routing, repeater insertion, and choice ofshielding/spacing rules for signal integrity and performance. We address four basicquestions. (1) How should width and spacing be allocated to maximize performance fora given line pitch? (2) For a given line pitch, what criteria affect the optimal interval atwhich repeaters Should be inserted into global interconnects? (3) Under what circumstancesare shield wires the optimum technique for improving interconnect performance?(4) In global interconnect with repeaters, what other interconnect tuning is possible?Our study of question (4) demonstrates a new approach of offsetting repeater placementsthat can reduce worst-case cross-chip delays by over 30% in current technologies