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Impulse: Memory System Support for Scientific Applications
Author(s) -
John B. Carter,
Wilson C. Hsieh,
Leigh Stoller,
M. Swanson,
Lixin Zhang,
Sally A. McKee
Publication year - 1999
Publication title -
scientific programming
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.269
H-Index - 36
eISSN - 1875-919X
pISSN - 1058-9244
DOI - 10.1155/1999/209416
Subject(s) - computer science , memory controller , interleaved memory , cache only memory architecture , physical address , impulse (physics) , cache , embedded system , cas latency , parallel computing , registered memory , uniform memory access , memory map , latency (audio) , computer hardware , computer architecture , cpu cache , semiconductor memory , memory management , cache coloring , telecommunications , physics , quantum mechanics
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application‐specific optimizations through configurable physical address remapping. By remapping physical addresses, applications control how their data is accessed and cached, improving their cache and bus utilization. Second, Impulse supports prefetching at the memory controller, which can hide much of the latency of DRAM accesses. Because it requires no modification to processor, cache, or bus designs, Impulse can be adopted in conventional systems. In this paper we describe the design of the Impulse architecture, and show how an Impulse memory system can improve the performance of memory‐bound scientific applications. For instance, Impulse decreases the running time of the NAS conjugate gradient benchmark by 67%. We expect that Impulse will also benefit regularly strided, memory‐bound applications of commercial importance, such as database and multimedia programs

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