Principles for Language Extensions to VHDL to Support High-Level Modeling

This paper reviews proposals for extensions to VHDL to support high-level modelingand places them within a taxonomy that describes the modeling requirements theyaddress. Many of the proposals focus on object-oriented extensions, whereas this paperargues that extension of VHDL to support high-level modeling requires a broaderreview. The paper presents a detailed discussion of issues to be considered in addinghigh-level modeling extensions to VHDL, including concurrency and communication,abstraction using entity interfaces, object-oriented data modeling, encapsulation, signalassignment semantics, shared variables, multiple inheritance, genericity and synthesis.Emphasis is placed on the importance of designing simple orthogonal semanticmechanisms that interact in well defined ways, and that integrate cleanly with existinglanguage features