A High Level Synthesis System for VLSI Image Processing Applications

We present a VLSI synthesis environment dedicated to the design of image processingarchitectures. The environment includes a “front-end” data-flow emulator for validationof the algorithms and the RTL-synthesis system called ALPHA. The latter implements astochastic search in the design space and produces efficient solutions considering the“restricted” domain of concerned applications. Two simulated Annealing (SA) algorithmsrun in sequence for data-path synthesis (scheduling and module selection) and thenfor control synthesis and data-path completion (binding). An interesting feature of thefirst optimization is the use of the data-flow graph regularity to predict the controlinfluence in terms of the future design. A few designs have already been compiled underthis environment including a default detector presented here