Architectural Power Estimation Based on Behavior Level Profiling

High level synthesis is the process of generating register transfer (RT) level designs frombehavioral specifications. High level synthesis systems have traditionally taken intoaccount such constraints as area, clock period and throughput time. Many high levelsynthesis systems [1] permit generation of many alternative RT level designs meetingthese constraints in a relatively short time. If it is possible to accurately estimate thepower consumption of RT level designs, then a low power design from among thesealternatives can be selected