Characterization of Catastrophic Faults in Reconfigurable Systolic Arrays

A common technique widely used to achieve fault tolerance in systolic arrays consists inincorporating in the array additional processing elements (PEs) and extra bypass links.Given a sufficient number of PEs and a large enough set of bypass links, it might seemthat the array can easily tolerate a large number of faults provided they do not occur inconsecutive locations. It is not always the case as shown in this paper. In fact, certainfault patterns exist and may occur which would prevent any kind of restructuring of thearay, thus making the structure unusable. For a given set of bypass links from each PEin the array, it is possible to identify such fault patterns which will prevent anyreconfiguration. In this paper, we identify the class of fault patterns that arecatastrophic for linear systolic arrays, examine their characteristics, and describe amethod for constructing such fault patterns