Timing-Driven Circuit Implementation

We consider the problem of selecting the proper implementation of each circuit modulefrom a cell library to minimize the propagation delay along every path from any primary input to any primary output subject to an upper bound on the total area of the circuit.Different module implementations may have different areas and delays on the paths. Wcshow that the latter problem is NP-hard even for directed acyclic graphs with twoimplementations per module and no restrictions on the overall area of the circuit. Wcpresent a novel retiming based heuristic for determining the minimum clock period onsequential circuits. Although our heuristics may handle a bound on the total area of thecircuit, emphasis is given on the timing issue