Statistical Estimation of the ,Switching Activity in VLSI Circuits

Higher levels of integration have led to a generation of integrated circuits for whichpower dissipation and reliability are major design concerns. In CMOS circuits, both ofthese problems are directly related to the extent of circuit switching activity. The averagenumber of transitions per second at a circuit node is a measure of switching activity thathas been called the transition density. This paper presents a statistical simulationtechnique to estimate individual node transition densities in combinational logiccircuits. The strength of this approach is that the desired accuracy and confidence can bespecified up-front by the user. Another key feature is the classification of nodes into twocategories: regular- and low-density nodes. Regular-density nodes are certified withuser-specified percentage error and confidence levels. Low-density nodes are certifiedwith an absolute error, with the same confidence. This speeds convergence whilesacrificing percentage accuracy only on nodes which contribute little to powerdissipation and have few reliability problems