SCOAP-based Testability Analysis from Hierarchical Netlists

Circuits of VLSI complexity are designed using modules such as adders, multipliers,register files, memories, multiplexers, and busses. During the high-level design of such acircuit, it is important to be able to consider several alternative designs and comparethem on counts of area, performance, and testability. While tools exist for area anddelay estimation of module-level circuits, most of the testability analysis tools work ongate-level descriptions of the circuit. Thus an expensive operation of flattening thecircuit becomes necessary to carry out testability analysis. In this paper, we describe atime and space-efficient technique for evaluating the well known SCOAP testabilitymeasure of a circuit from its hierarchical description with two or more levels ofhierarchy. We introduce the notion of SCOAP Expression Diagrams for functionalmodules, which can be precomputed and stored as part of the module data base. Ourhierarchical testability analysis program, HISCOAP, reads the SCOAP expressiondiagrams for the modules used in the circuit, and evaluates the SCOAP measure in asystematic manner. The program has been implemented on a Sun/SPARC workstation,and we present results on several benchmark circuits, both combinational andsequential. We show that our algorithm also has a straightforward parallel realization